The demand for higher performance, microcontroller-based products for use in communication and processing applications continues to increase rapidly. As a result, microcontroller-based product manufacturers are requiring the components and devices within these products to be continually improved to meet the design requirements of a myriad of emerging audio, video and imaging applications.
These microcontroller-based products use various types of processors, for example, general purpose microprocessors for controlling the logic of various digital devices, such as clock radios, microwave ovens, digital video recorders and the like, and special purpose microprocessors, such as math coprocessors for mathematical computations, or digital signal processors used in manipulating various types of information, including sound, imaging and video information.
The microcontroller typically includes a central processing unit (CPU) core for the processing functions, and a bus interface for communication with the various memory devices as well as external or other peripheral devices. For the storage of data and instructions, the microprocessor can include various types of memory. For example, the CPU for the microcontroller may include Random Access Memory (RAM) as well as Read-Only Memory (ROM), i.e., programmed memory. In addition, the microcontroller can also include flash memory which can be erased and reprogrammed in blocks instead of being programmed one byte at a time.
For the transmitting and receiving of data between various devices and components, microprocessors and other devices may utilize various types of serial interfaces. One such type of interface typically used is the serial peripheral interface (SPI). The microprocessors also generally utilize one or more buffers for the temporary storage of data, for example, to permit the microprocessors to manipulate the data before transferring the data through the SPI to another device. These buffers are configured with the SPI's to enable the processors to transmit and receive data to and from the buffers as needed in an application.
An embedded system is a specialized computer system that is part of a larger system or machine. Typically, an embedded system is housed on a single microprocessor board with the programs stored in either ROM or FLASH memory. Some embedded systems include an operating system, but many are so specialized that the entire logic can be implemented as a single program.
In embedded microcontroller systems, the peripheral devices can be accessed by the CPU via a bus interface using a bus architecture, for example, a tristate bus architecture. There are a number of disadvantages associated with the tristate bus architecture. For example, in a tristate bus architecture, when a peripheral device is not being accessed, the peripheral device will provide a high impedance output to the bus. This characteristic is not desirable for a design for test (DFT) product because the high impedance makes it difficult to test the disabled tristate buffers. Furthermore, the high impedance signal can cause errors in the values tested. In addition, if no peripheral device is driving the bus, the resulting floating node will cause high leakage current. Moreover, if more than one peripheral is driving the bus, a short circuit current can result. Additionally, the tristate buffer architecture can cause a slow down in the transfer of information.
One approach that attempts to reduce the inadequacies associated with tristate bus architectures includes the implementation of bus keepers attached to the bus. Bus keepers are configured such that until the bus is driven with a different logic value, the bus keeper forces the bus to retain its previous logic value. Although the bus keeper approach may solve the floating node problem, the disabled tristate buffers are still very difficult to test. In addition, the tristate buffers need to be strong enough to “snap” the bus keeper, i.e., if the voltage on the bus is driven beyond a voltage threshold, the drivers can overcome the bus keeper device and cause it to hold the new logic value. For example, the bus might hold “0” (logic low voltage) until a “1” (logic high voltage) is driven to the bus by a sufficiently strong driver. Because snapping the bus keeper requires powerful drivers in the peripheral devices, a larger chip area and high power consumption is also required by this solution.
With reference to FIG. 2, a typical prior art CPU—Bus Interface (Bus IF)-Peripheral configuration is described in more detail. CPU 102 communicates through Bus IF 204 to communicate with one or more peripheral devices such as a first peripheral device (P1) 201, and a second peripheral device (P2) 202, through an Nth peripheral device (PN) 209. Generally, the peripheral devices communicate with CPU 102, and not with each other, through Bus IF 204. However, direct memory access (DMA) techniques also allow peripheral devices to communicate with memory without communicating with the CPU.
Bus IF 204 includes a transmitter 210 and receiver 212 which are connected over a common bus 220 to individual transmitters and receivers in the connected peripheral devices. For example, first peripheral device P1 contains transmitter P1T 231 and receiver P1R 241; second peripheral device P2 contains transmitter P2T 232 and receiver P1R 242; and Nth peripheral device PN contains transmitter PNT 239 and receiver PNR 249. The peripheral devices could be any type of peripheral device. CPU 102 provides signals 250 to Bus IF 204 commanding Bus IF 204 and the peripherals to perform a “read” or “write” operation, and identifying the appropriate peripheral device with which CPU 102 is to communicate. The peripheral device is identified via address lines, not shown, which provide enabling/disabling signals to the peripheral devices to enable the correct peripheral device for communication with CPU 102.
The transmitter 210 in Bus IF 204 and the transmitters (e.g. 231, 232, 239) in the peripheral devices are tristate transmitters. When enabled, the transmitters drive a signal comprising 1's and 0's to the common bus 220. When disabled, the transmitters provide a high impedance, Z state to the common bus 220. Because the transmitters and receivers share a common bus, when one transmitter is “talking”, the other transmitters must “remain silent.” If two transmitters were to talk at the same time, the transmission would most likely be garbled because the transmitters may be attempting to simultaneously drive both high and low voltages onto the same bus.
This tristate bus architecture gives rise to several problems as discussed above. For example, this architecture results in high power consumption. CMOS devices use relatively low amounts of power while holding a “1” or “0”; however, relatively large amounts of power are consumed while switching a CMOS device, or when the CMOS device is exposed to a high impedance Z state. If no devices are driving common bus 220, another high Z state arises. If no peripheral device is driving or receiving, the resulting floating node can cause high leakage current. When high power consumption occurs, the constant current flow also shortens the life of the device.
Moreover, if more than one peripheral is driving the bus, an undesirable short circuit current can result. This occurs, for example, when one device drives a “1” and the other device drives a “0”, causing a high current to run between the high voltage and low voltage. It is also undesirable to have two transmitters sending data at the same time because of the possibility of scrambling the signal that should have been sent. Some microprocessors, however, have small possible overlaps between one device turning on and another device turning off The small overlaps cause short circuits. These short circuits may be avoided by providing a short time period between the moment when a first transmitter turns off and when a second transmitter turns on. Unfortunately, this time period results in unnecessary delay, thus slowing down the processing speed of the microprocessor.
The inclusion of a time gap between the transmissions of two different transmitters also gives rise, again, to the floating node condition where no device is driving common bus 220, and thus causes the high impedance Z state. To combat this problem, bus keepers have been added to the microcontrollers. For example, bus keeper 260 is provided in communication with common bus 220. Bus keeper 260 holds the last value on bus 220 until a new value is driven on bus 220. A disadvantage accompanying bus keeper 260 is that the tristate drivers need to be strong enough to snap the bus keeper; and therefore stronger drivers are required, resulting in a larger chip area and higher power consumption.
Another disadvantage of the presence of a high Z state is that it is difficult to test the circuit. It should be clear that in order to fully test the communication functions between the peripherals and the CPU, the tristate buffers need to be tested in their disabled state as well as when transmitting ones and zeros. It is desirable during testing that when one transmitter is transmitting data, the other transmitters can and do stay disabled. However, when these transmitter devices are disabled, a resulting floating node arises (a high Z state), and it is difficult to test for that condition.
Accordingly, a need exists for an improved embedded system bus architecture that solves the above problems. In addition, a need exists for an improved embedded system bus architecture that also facilitates high test coverage without the high power requirements and large area requirements.